Kontakt
Jak nakupovat
Doručení
Nákupní rádce
Angličtina
173 b
Až 30 dní na vrácení zboží
Zákazníci také koupili
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs. "ASIC and FPGA Verification: A Guide to Component Modeling" expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. This book provides numerous models and a clearly defined methodology for performing board-level simulation. It covers the details of modeling for verification of both logic and timing. This is the first book to collect and teach techniques for using VHDL to model 'off-the-shelf' or 'IP' digital components for use in FPGA and board-level design verification.
Informace o knize
Angličtina
Darujte tuto knihu ještě dnes
Je to snadné
1 Přidejte knihu do košíku a zvolte doručit jako dárek 2 Obratem vám zašleme poukaz 3 Kniha dorazí na adresu obdarovanéhoMohlo by vás také zajímat
/
Brožovaná
641
Kč
/
Brožovaná
362
Kč
/
Brožovaná
1 642
Kč
Ahoj! Jsem Libroamiko, tvůj knižní rádce.
Jak ti můžu pomoct?