FPGA Accelerated Features Extraction

Real time image processing is gaining momentum in fields such as medicine, aeronautics, human computer interaction and many others, gradually spreading new horizons towards smooth and fast control and intelligent systems. Remarkable rates of 200/300 processed frames per second can be achieved merely through the use of dedicated ASICs or FPGAs. Understanding an image contents is a step-by-step process, accomplished by extracting application-specific features, also named descriptors, and employing a classifier to infer the information they convey. However, in most of the cases, it is necessary to adapt the feature set to the best performing combination and to improve the descriptors resilience by making them acquire robustness properties against image translation, rotation or scale. The latter are important prerequisite for successful classification. The descriptors choice may vary in time, thus requiring the hardware designer to possibly re-engineer entire architectures to expand or shrink the set. We introduce a versatile design framework, that makes it possible to easily update the set cardinality and operate on its contents without having to re-engineer an entire project.