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the predictable decrease of transistors sizes which is nowadays close to the atomistic dimension leads today to nanoscale devices. Double gate MOSFETs are considered to be one of the most promising candidates for nanoscale CMOS devises. It might be the best viable alternative to build nano MOSFETs when Lg50 nm and it is well known that, in practice gate length in BULK MOSFETs are scaled to below 50 nm and gate lengths of experimental FETs have approached currently 15 nm. DG MOSFETs demonstrated a perfect electrostatic control, a better control of the gate region with a reduction of short channel effects and a greater scalability. Transistors design parameters strongly affect the drain current. Our contribution, in this work focuses on the study a planar DG n-MOSFET parameters variation upon its electrical properties. Simulation results we obtained having a direct impact on our transistor drain current are relating to the influence of some parameters variation have been performed using SILVACO software and are very promissing. These simulation results allow to design an optimized device.
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