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System Level ESD Protection
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This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. Coverage focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and chip-system co-design. Readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) to meet system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design, using a detailed structural description of the IC-level test methods and the correlation between IC-level and system-level test results. The IC-level ESD protection design is demonstrated with representative case studies and is based on numerical simulation and test chip experimentation. The overall methodology for chip-system level ESD co-design is presented as a step-by-step procedure that involves both ESD testing and analysis, based on numerical simulations.
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